Firmware for synchronizing chip-scale atomic clock to GPS

This master thesis is conducted as the final research project in the master program Embedded Electronic System Design at Chalmers University of Technology, Gothenburg. The research is done for the Norwegian Defence Research Establishment (FFI) whic has formulated the problem definition. The thesis is a case study of firmware development for synchronization of a Chip- Scale Atomic Clock (CSAC) to global positioning system (GPS). The work is intended to solve the major firmware related research and development, necessary to integrate a GPS synchronized, CSAC driven timekeeping system, to FFI’s Networked Intelligent Underwater Sensors (NILUS) demonstrator system. Symmetricom introduced in 2011 the world’s first commercial available Chip-Scale Atomic Clock, which improved size, performance and power consumption by orders of magnitude compared to available technology. In 2015, the CSAC is still the leading edge for precise and accurate timekeeping in mobile applications. By combining the performance and features of CSAC and GPS technology, FFI is hoping to drastically improve synchronization in the NILUS network, which would increase the system performance, and possible open up for new applications. The overall goal of the thesis is to design, implement and evaluate firmware for a newly developed prototype board, the "CSAC board". The focus is on providing a reliable solution that has as good time accuracy and precision as the hardware allows. A bare-metal firmware solution with the important core features has been implemented and tested. The implemented design provides a solution that is capable of synchronizing independent nodes within ± 200 ns, and with an frequency accuracy as small as 3.6 × 10−10. It can capture external asynchronous signals and generate absolute timestamps with a resolution of 100 ns. New challenges and possibilities have been discovered through research and experimentation, valuable for the main developers to start final development and system integration. Both the firmware design and underlying hardware design have been shown to be well suited for the task, and a final solution based on this design is recommended.